1. Field of the Invention
The present invention relates to level shifters and, more particularly, to a high-speed level shifter.
2. Description of the Related Art
A level shifter is a common circuit device that is used to translate a voltage from a first voltage level to a second voltage level. For example, deep sub-micron digital circuits represent a logic one with a voltage of approximately 1.2 volts. When these circuits communicate with other circuits that represent a logic one with a voltage of approximately 3.6 volts, a level shifter is used to shift the 1.2 volt level to a 3.6 volt level.
FIG. 1 shows a circuit diagram that illustrates an example of a prior art level shifter 100. As shown in FIG. 1, level shifter 100 includes an input stage 110 that receives an input digital signal IN, and outputs an inverted input signal INV and a non-inverted input signal IVM. Input stage 110 has a first inverter IV1 that inverts the input digital voltage IN and outputs the inverted input signal INV, and a second inverter IV2 that inverts the inverted input signal INV and outputs the non-inverted input signal IVN.
First inverter IV1 includes a PMOS transistor M36 that has a source connected to a first power supply VDD1, such as 1.2V, a drain, and a gate connected to receive the input signal IN. In addition, first inverter IV1 also includes an NMOS transistor M35 that has a source connected to ground, a drain connected to the drain of PMOS transistor M36, and a gate connected to receive the input signal IN.
Second inverter IV2 includes a PMOS transistor M25 that has a source connected to the first power supply VDD1, a drain, and a gate connected to receive the output of inverter IV1. In addition, second inverter IV2 also includes an NMOS transistor M24 that has a source connected to ground, a drain connected to the drain of PMOS transistor M24, and a gate connected to output of inverter IV1.
Level shifter 100 also includes a pull-down stage 112 that pulls down the voltage on a first intermediate node NIM1 when the input voltage IN is a logic low (e.g., zero volts) and the inverted input voltage INV is a logic high (e.g., 1.2V). Level shifter 100 also pulls down the voltage on a second intermediate node NIM2 when the input voltage IN is a logic high (e.g. 1.2 volts) and the non-inverted signal IVM is a logic high.
Pull down stage 112 includes a NMOS transistor M38 and a NMOS transistor M39. NMOS transistor M38 has a source connected to ground, a drain connected to the first intermediate node NIM1, and a gate connected to the drains of transistors M35 and 36 of inverter IV1. NMOS transistor M39 has a source connected to ground, a drain connected to the second intermediate node NIM2, and a gate and the drains of transistors M25 and 24 of inverter IV2.
Level shifter 100 also includes a cross-coupled pull-up stage 114 that pulls up the voltage on the first intermediate node NIM1 to a level shifted voltage (e.g., 3.6 volts) when the input voltage IN is a logic high. Stage 114 also pulls up the voltage on the second intermediate node NIM2 to the level shifted voltage when the input voltage IN is a logic low.
Pull up stage 114 includes a PMOS transistor M14 and a PMOS transistor M13. PMOS transistor M14 has a source connected to a second power supply VDD2 (e.g., 3.6 volts), a drain connected to the first intermediate node NIM1, and a gate connected to the second intermediate node NIM2. PMOS transistor M13 has a source connected to the second power supply VDD2, a drain connected to the second intermediate node NIM2, and a gate connected to the first intermediate node NIM1.
Level shifter 100 also includes a buffer output stage 116 that is connected to the second intermediate node NIM2, and an inverting output stage 118 that is connected to the first intermediate node NIM1. Output stage 116 includes a third inverter IV3 that inverts the voltage on the second intermediate node NIM2, and a fourth inverter IV4 that inverts the voltage output from inverter IV3.
Third inverter IV3 includes a PMOS transistor M49 that has a source connected to the power supply VDD2, a drain, and a gate connected to receive the signal on the second intermediate node NIM2. In addition, third inverter IV3 also includes an NMOS transistor M48 that has a source connected to ground, a drain connected to the drain of PMOS transistor M49, and a gate connected to receive the signal on the second intermediate node NIM2.
Fourth inverter IV4 includes a PMOS transistor M31 that has a source connected to the second power supply VDD2, a drain, and a gate connected to receive the output of inverter IV3. In addition, second inverter IV4 also includes an NMOS transistor M30 that has a source connected to ground, a drain connected to the drain of PMOS transistor M31, and a gate connected to output of inverter IV3.
Output stage 118 includes a fifth inverter IV5 that inverts the voltage on the first intermediate node NIM1. Fifth inverter IV5 includes a PMOS transistor M52 that has a source connected to the power supply VDD2, a drain, and a gate connected to receive the signal on the first intermediate node NIM1.
In addition, fifth inverter IV5 also includes an NMOS transistor M53 that has a source connected to ground, a drain connected to the drain of PMOS transistor M52, and a gate connected to receive the signal on the first intermediate node NIM1. Inverter IV5 also provides balance such that the first and second intermediate nodes NIM1 and NIM2 see the same load.
In operation, when the input voltage IN is a logic low, transistor M38 turns on in response to the logic high of the inverted input signal INV, and pulls the voltage on the first intermediate node NIM1 to ground. Transistor M39, on the other hand, turns off in response to the logic low of the non-inverted input signal IVM. Since the gate of PMOS transistor M13 is also connected to the first intermediate node NIM1, the falling voltage turns on transistor M13, thereby pulling up the voltage on the second intermediate node NIM2.
In addition, inverter IV5 inverts the logic low on the first intermediate node NIM1 to drive a logic high at the level shifted voltage, e.g., 3.6 volts. Further, inverter IV3 inverts the logic high on the second intermediate node NIM2, and inverter IV4 inverts the output of inverter IV3 to drive a logic high at the level shifted voltage.
Similarly, when the input voltage IN is a logic high, transistor M39 turns on in response to the logic high of the non-inverted input signal IVM, and pulls the voltage on the second intermediate node NIM2 to ground. Transistor M38, on the other hand, turns off in response to the logic low of the inverted input signal INV. Since the gate of PMOS transistor M14 is also connected to the second intermediate node NIM2, the falling voltage turns on transistor M14, thereby pulling up the voltage on the first intermediate node NIM1.
In addition, inverter IV5 inverts the logic high on the first intermediate node NIM1 to drive a logic low. Further, inverter IV3 inverts the logic low on the second intermediate node NIM2, and inverter IV4 inverts the output of inverter IV3 to drive a logic low.
One limitation of level shifter 100 is that level shifter 100 works poorly in high-speed applications. Thus, there is a need for a high-speed level shifter.